1/2-inch 7.2MPixel CMOS Image Sensor with 2.25μm Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation

摘要

In recent years, the market for CMOS image sensors (CIS) have been rapidly growing in several high-volume applications, such as mobile phones, digital still cameras (DSC), and camcorders. This growth in not only due to the ability to integrate sensing array with analog- and digital-processing circuits in CMOS, hut also the persistently improving image quality of CIS that is comparable to that of CCD [1]. In addition, the pixel size of CIS has been reduced and become comparable to CCD with the help of pixel-sharing architecture that results in the high capacity of photodiode and thus, the high SNR even with the small-size pixel. Although the image quality and the pixel size of CIS are comparable to CCD, the SNR of CIS under the preview and sub-sampling operation for recording a moving object is not as good as that of CCD. This is because the signal charge of CCD under sub-sampling mode can be added up at the vertical-CCD stage and thus, the SNR increases compared with full-resolution mode whereas that is not the case for previously reported CIS. In this paper, a 1/2-inch 7.2MPixel CIS with 2.25μm pixel is described using 4-shared pixel structure realizing pixel-level charge summation function, similar to CCD. This resulting pixel having 57% fill factor shows full well capacity of 14,000e{sup}- with SNR{sub}(max) of 41dB under the full-resolution operation, and an additional 6dB increment of SNR by the pixel-level charge summation under sub-sampling operation. A Cu process with 0.13μm design rule and a low-noise process technology are employed for high sensitivity of 15,000e{sup}-/lux.s and low noise of 8e{sup}-, respectively.