A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners

摘要

There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of −98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].