A 15Bits 12MS/s 5th-Order Sigma-Delta Modulator for Communication Applications

摘要

In this paper a 5th-Order single-loop Sigma-Delta Modulator with combination of low distortion and hybrid structures is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feed-forward paths and modulator coefficients. Thus, its sensitivity to coefficient mismatching is reduced. To lower the power consumption of the modulator, the IIR filter block is implemented by single OTA, and a passive adder is used to realize input quantizer adder. Simulation results show that this structure can achieve 15-bit of resolution and 6MHz input signal bandwidth, with 12V supply voltage using a 0.13μm CMOS technology. Power consumption of modulator is 53mW.