A New Low Latency Parallel Turbo Decoder Employing Parallel Phase Decoding Method

摘要

In this paper, a new parallel phase algorithm for parallel turbo decoder is proposed. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. For verifying the proposed parallel phase turbo decoder, we have used FPGA to emulate the hardware architectures, and designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. The gate count of this decoder chip is 128284. The chip size including I/O pad is 1.91×1.91mm~2. The simulation result shows that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.23%～58.13% decoding time saved, with 8 iteration times at 100MHz working frequency.