THE DEVELOPMENT OF INTEGRATED ENGINEERING TOOL (SafeCASE-PLC) FOR SAFETY GRADE PLC

摘要

Regarding digitalizing the Nuclear Instrumentation and Control Systems, the application program responsible for the safety functions of Nuclear I&C Systems shall ensure the robustness of the safety function through development, testing, and validation roles for a life cycle process during the software development. The importance of software in nuclear systems is increasing continuously. Integrated engineering tools to develop, test, and validate safety application programs require increasingly more complex parts among a number of components within nuclear digital I&C systems. This paper introduces an integrated engineering tool, SafeCASE-PLC, which is being developed by our project and also presents a common platform, testing strategy, and validation methods implemented in the SafeCASE-PLC. A common platform means a framework to integrate the CASE-TOOL which can develop, test, and validate the software for the I&C System of a nuclear facility. The platform for the SafeCASE-PLC uses the framework based on JAVA-Eclipse. It integrates the industrial development tools supporting Function Block Diagram (FBD) languages onto its framework. The SafeCASE-PLC supports the sub-module to translate the FBD languages into C languages and includes a plug-in software tool that can test C languages. On the contrary, we also research the methods that can test directly the application generated using FBD languages. The newly generated application program can be tested directly without converting into C language. It is possible to test the application program directly as well as indirectly. The two testing results from the C tester and the FBD tester can be utilized for ensuring a quality feature of the translator that can convert the FBD application to C language code. The SafeCASE-PLC includes a utility that can verify some applications formally. The utility translates the FBD program into the Verilog Program. It performs an equivalence check and model check using formal verification tools such as VIS and SMV. The equivalence check of a VIS can prove the equality of the FBD program and Verilog program. The model checking function of an SMV can also prove whether the FBD program satisfies the verification attribute mathematically.