Efficient multi-domain ESD analysis and verification for large SoC designs

摘要

An efficient layout-based multi-domain ESD analysis and verification method has been developed for large SoC designs containing thousands of bumps. A fast resistance and current density check for ESD discharging paths across multiple diodes/clamps represented as I-V curves is performed, including on-chip signal/power/ground/package grid. Real application examples are shown.