Parametric study of dead time effect on three phase AC output impedance of Voltage Source Inverter (VSI)

摘要

This paper reports that the output impedance of a VSI measured in experiments differs from the results derived from the traditional small-signal model known in the literature. A parametric study of this effect is conducted by simulation, and then verified by experiment. The result reveals that dead time is the main contributor to the difference in impedance between simulation and experimentation. Dead time adds a resistive part to the VSI output impedance.