Space vector modulation scheme to minimize common-mode voltage generated by a three-phase hybrid multilevel inverter

摘要

This paper proposes the implementation of a space vector modulation (SVM) scheme to reduce the common-mode voltage of a symmetrical hybrid five-level inverter operating at high modulation index. The proposed modulation is implemented in a DSC-Digital Signal Controller. It employs vectors that prevent voltage vectors that impose high common-mode voltages at the converter load. Experimental results are presented in order to validate the proposed modulation scheme.