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On experimental research of efficiency of tests construction for combinational circuits by the focused search method

机译:集中搜索法研究组合电路测试构造效率的实验研究

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Consider the possibility reducing the iteration value in building complete validation tests for digital devices. Building a test for a given fault is reduced to searching the terminal node in the signals assignment tree. The reducing is achieved by accumulating and using of information about dead-end conditions to avoid similar situations in the earlier stages. Allows any faults that can be described by logical functions.
机译:在构建针对数字设备的完整验证测试时,请考虑降低迭代值的可能性。为给定故障建立测试的过程被简化为在信号分配树中搜索终端节点。通过累积和使用有关死角条件的信息来避免早期阶段的类似情况,从而实现了减少。允许通过逻辑功能描述的任何故障。

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