Subthreshold MOS dynamic translinear neural and synaptic conductance

摘要

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is practical realization of complex conductance-based models of biophysical neural and synaptic dynamics in nanoscale electronics. Here we present such highly compact and low-power realizations, where each conductance is implemented using a single MOS transistor operating in subthreshold. Three alternative realizations are shown, implementing log-domain transformations of the conductance-based dynamics using translinear current scaling, capacitance scaling, and voltage scaling. Transistor level simulations validate the linearity of single transistor neural and synaptic conductance-capacitance dynamics in a 90nm CMOS process.