The Simulation and Research on Zero-Vector PWM Common-mode Voltage Suppression in Diode-clamped Five-level Converters

摘要

common-mode voltage (CMV) produced in high voltage large power converter causes great concern for more researchers. A novel common-mode voltage suppression scheme based on zero-vector PWM strategy (ZVPWM) is present in this paper. Taking a diode-clamped fivelevel converter as example, the principle of zero vector PWM common-mode voltage (ZCMVPWM) suppression method is studied in detail. ZCMVPWM suppression strategy is including four important parts, which are locating the sector of reference voltage vector, locating the small triangular subsector of reference voltage vector, reference vector synthesis, and calculating the operating time of vector. The principles of four important pars are illustrated in detail and the corresponding MATLAB models are established. System simulation and experimental results are provided. It gives some consultation value for the development and research of multi-level converters and is helpful to further promote the use of high voltage large power converters.