Design of Micropower Consumption and High Linearity Voltage to Frequency Converter Using CMOS Technology

摘要

A kind of 0.25 μm CMOS VFC was designed, which included voltage to current converter (VCC), charge and discharge circuit (CDC) and voltage testing circuit (VTC). To reduce power consunption and improve linearity, two-stage low voltage cascode was used in VCC while a CMOS electronic switching cell (ESC) and a novel CMOS feedback gate circuit (FGC) was adopted in VTC. The circuit structure was modified and the layout design was optimized. The simulation and hardware circuit experiments were carried out. These experiment results show that the linear range of output frequency is 0-60.5 MHz given a 0~9 V input range. The error in linearity is better than 1%, and the power consumption is only 203 μW. With these characteristics, this converter is very suitable for micropower consumption and high linearity digital measurement systems.