A LOW-POWER DESIGN OF QUANTIZATION FOR H.264 VIDEO CODING STANDARD

摘要

Low-power quantization architecture for H.264/AVC is presented and implemented on VLSI. The multiplication operation is replaced with shifts and additions. Similar designs were proposed which had 75.2% area and 76.3% power on average saved compared with original H.264 quantization scheme, along with an error percent within 6.4% range. In this paper, the improved architecture has error percent within 2.4% range. The power and area saved on average is ～8% compared to designs of similar architecture.