Design and Implementation of a Shared Buffer Architecture for a Gigabit Ethernet Packet Switch

摘要

In this paper, we explore the design issues of a shared buffer architecture capable of buffering fixed and variable sized packets for a 10G Ethernet switch. We present the design and implementation of a shared buffer circuit based on Xilinx Virtex 4 FPGA technology. The proposed architecture is economic from the resource sharing point of view and is capable of supporting buffer bandwidths in excess of 31 Gbps using standard FPGA technology.