Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study

摘要

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.