This paper proposes a Decision Feedback Equalizer (DFE) with an error feedback filter using the Multi-Modulus Algorithm (MMA). The proposed equalizer has been designed for 64/256 QAM modulations. The proposed DFE adds the error feedback filter to the DFE structure to improve the channel adaptive performance. We have simulated the proposed equalizers using the Cadence SPW CAD tool. The architecture has been modeled by VHDL and logic synthesis has been performed using the 0.25 μm Faraday library. The total gate count of the proposed equalizer is about 190,000 and the operating frequency is 15 MHz. The proposed equalizers provide the symbol rate up to 64 Mbps
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