A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair

摘要

A high speed, low delay/log(ΔVin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(ΔVin) of the comparator is 22ps/dec and consumes 213µW at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.