A digital beamforming processor for the joint DoD/NASA space based radar mission

摘要

The space based radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-earth orbiting, 2/spl times/50 m L-band (1.26 GHz) radar system for both Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller sub-antenna panels in the array and the on-board processing electronics for synthetic aperture radar (SAR) and moving target indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the algorithmically simple yet computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07/spl deg/ rms phase precision per channel, -39.0 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.