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A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator

机译:一个9µW 88dB DR全时钟开关运算ΔΣ调制器,具有新颖的功率和面积高效谐振器

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A 9µW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35µm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance, a novel resonator idea applicable to SO technique is adopted to realize a coefficient of 1/100 with 75% power and 70% area reduction over the conventional design. The FOM of the designed modulator is highest among the collected recent low power modulators.
机译:9µW 88dB DR开关运算放大器(SO)ΔΣ调制器采用低成本0.35µm CMOS工艺实现。为了清楚地评估有限电压增益和1 / f噪声的影响,引入了两种高效的方法。为了降低总功耗,还提出了一种新的完全关闭的SO,该功耗可节省50%的功率,并且具有比传统类型高的两倍的品质因数(FOM)。此外,为了提高性能,采用了一种适用于SO技术的新型谐振器思想,与传统设计相比,可实现系数为1/100且功率降低75%,面积减少70%的设计。在最近收集的低功耗调制器中,设计调制器的FOM最高。

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