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Setup time, hold time and clock-to-Q delay computation under dynamic supply noise

机译:动态电源噪声下的建立时间,保持时间和时钟至Q延迟计算

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This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold time on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.
机译:本文讨论了如何在FF时序估计中应对动态电源噪声。我们首先回顾建立时间和保持时间对电源电压的依赖性,并指出建立时间比电源保持时间和标称电压下的保持时间对电源电压更为敏感。因此,我们提出了一种使用等效直流电压方法考虑给定电压降波形来估算建立时间和时钟至Q延迟的程序。实验结果表明,所提出的程序可以很好地估计建立时间和时钟到Q的延迟波动,平均误差为5%和3%。

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