Comparative analysis of power stage losses for synchronous Buck converter in Diode Emulation mode vs. Continuous Conduction Mode at light load condition

摘要

Light load efficiency attracts more attention nowadays and its requirement becomes stringent. To improve the light load efficiency in a synchronous Buck converter, several methods, such as pulse skipping, constant on-time, and Diode Emulation (DE), can be used. Compared to other methods, DE has the advantage of keeping its switching frequency unchanged and simple control circuits. Previous literatures present power loss estimation of DE in an ideal case, when Synchronous Field Effect Transistor (FET) is turned off at inductor current zero-crossing point. However, there is always deviation in practical circuit realization and this deviation may cause efficiency to drop by up to 2%. This paper first presents the comparative power stage loss analysis in DE vs. Continuous Conduction Mode (CCM) operation, then investigates the non-ideal DE situation, and follows with the extra power loss estimation. Simulation and experimental results verify the validity of the analysis.