Clock routing for structured ASICs with via-configurable fabrics

摘要

In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental data show that a delay-balanced clock tree can be constructed using via-configurable routing fabric, with an average skew of 8.1% of clock latency for some benchmark circuits. Such a result is comparable to what can be achieved by a commercial clock tree synthesizer.