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A 2-Bit 4GS/s Flash A/D Converter in 0.18μm CMOS for an IR-UWB Communication System

机译:用于IR-UWB通信系统的0.18μmCMOS的2位4GS / s闪存A / D转换器

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A 4GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC,implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore,because of the low-bit-sampling characteristic of the IR-UWB system,non-time-interleaved structure is used without digital calibration which largely saves the power consumption,chip area and cost. And a differential resistive reference ladder is designed to minimize the inaccuracy of the reference voltage. The proposed ADC dissipates 34mW power from a 1.8V supply while operating at 4GHz. This chip has been fabricated in 0.18 μm 1P6M CMOS process and the ADC achieves 1.86-bit effective number of bits (ENOB) for input signal of lGHz at 4GS/s in simulation of FFT analysis.
机译:一个4GS / s 2位非时间交错闪存ADC设计用于IR-UWB(脉冲无线电超宽带)接收器。在该闪存ADC中,在模拟部分中实现差分低摆幅操作,在数字部分中实现CML(电流模式逻辑)会导致高速和低功耗。此外,由于IR-UWB系统的低位采样​​特性,使用了无时间交织的结构而无需进行数字校准,从而大大节省了功耗,芯片面积和成本。并且设计了差分电阻参考梯形图,以最大程度地减小参考电压的不准确性。拟议的ADC在4GHz下工作时,从1.8V电源消耗的功耗为34mW。该芯片采用0.18μm1P6M CMOS工艺制造,在FFT分析的仿真中,ADC以4GS / s的速率实现了1GHz输入信号的1.86位有效位数(ENOB)。

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