Accurate modeling of the systematic variation of copper interconnect thickness due to chemical mechanical polishing (CMP) is useful for providing designers and process engineers with information about potential functional yield issues, as well as timing impact from resistance and capacitance variation. Using accurate models of thickness variation can allow for tighter design cycles and lower guardbanding.This paper discusses the importance of having accurate information about the process steps before the copper interconnect processes, in order to further improve simulation accuracy. Specifically, the importance of simulating the full material stack involved in the semiconductor manufacturing process flow is discussed, with specific discussion of modeling the pre-metal dielectric (PMD) layer.
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