Dual-encoding BIST Design with Low Power Consumption Based on Clock Gating

摘要

Combining linear feedback shift register (LFSR) and Johnson folding counter, a dual-encoding built-in self-test (BIST) design with low power consumption based on clock gating is proposed. Firstly, folding counter feeds were encoded by LFSR, and secondly deterministic test patterns were generated by using the selected fold distance from ROM. Also,with the specialized encoder and clock gating, these test patterns were designed to form a pseudo single input change set, and the ineffective patterns were not act upon the circuit under test (CUT). This leads to prominent decreases of power consumption and redundant test patterns generated by different seeds, without losing stuck-at fault coverage.Experimental results based on ISCAS'85 and 89 benchmark circuits have demonstrated the efficiency of our approach.