In the chemical-mechanical polishing or planarization (CMP) process employed by the semiconductor industry, the coated wafers are polished face-down, In this "architecture", the polishing rate across a 300-mm wafer is non-uniform — primarily due to non-uniform slurry distribution at the wafer/pad interface. To compensate for the lack of wafer-scale polishing uniformity, therefore, such techniques as zonal pressure control and multi-step polishing are commonly implemented in practice. Nevertheless, Cu dishing and dielectric erosion still remain critical issues — in large part due to wafer-scale non-uniform polishing. Recently, we have proposed the face-up CMP architecture as an alternative for realizing a high degree of wafer-scale polishing uniformity, and thus minimizing Cu dishing and dielectric erosion. In this paper, a comprehensive theory of face-up polishing is presented in terms of contact geometry, kinematics, and slurry flow. Additionally, polishing experiments have been conducted on both blanket and patterned Cu wafers. Experimental results validate the face-up CMP theory fairly well.
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