A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

摘要

Power delivery is a growing reliability concern in micropro- cessors as the industry moves toward feature-rich, power- hungrier designs. To battle the ever-aggravating power con- sumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to oper- ate the processor within a given power envelope. These tech- niques, however, often lead to high-frequency current varia- tions, which can stress the power delivery system and jeop- ardize reliability due to inductive noise (Lrac{{di}} {{dt}} ) in the power supply network. To counteract these issues, modern mi- croprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capac- itance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a proces- sor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin dis- tribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current de- mand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0%.