A Fine-grained/Coarse-grained Heterogeneous Reconfigurable DSP Architecture Based on Parallel Processing

摘要

In order to accelerate the processing rate of most DSP(Digital Signal Processing) related algorithms, such as FFT, FIR, Vector operations, and graphic and image manipulations, while the adaptability of the chip is kept, a reconfigurable architecture (named ReDAr) for DSP combining the merits of DSP processors, Reconfigurable Computing and Parallel Processing is proposed, and applied to the Radar system of Automatic Navigation Instrument. By analyzing the computation structure of these algorithms and traditional architectures for DSP applications, the basic Processing Element (PE), Crossbar interconnect network, blocks of multi-port Memory organization, host controlling strategy, and data sequencing scheme of the architecture are conceived. Parts of the architecture, including the PE, Crossbar, data sequencer and I/O unit, have fine-grained or coarse-grained reconfigurability. After configuration, PEs and blocks of memory can be interconnected into a parallel and pipelined framework, which closely matches any one of the algorithms and acts like a dedicated hardware. By simulation, the performances of these algorithms mapped onto this architecture are comparative to algorithm specific chips in market, and satisfy the requirement of the targeted application.