A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

摘要

We have designed a 16-bit redundant binary multiplier using pass-transistor logic SPL on a 0.35 μm technology. Number of transistors is 12, 349, and area is 1, 322 μm ×332 μm. Measured power dissipation and maximum delay at T=25 °C and VDD=3.3V are 33.7 mW/100 MHz and 7.4 nsec, respectively.