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Learning-based prediction of embedded memory timing failures during initial floorplan design

机译:基于学习的嵌入式内存时序故障预测初始平面图设计中的预测

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Embedded memories are critical to success or failure of complex system-on-chip (SoC) products. They can be significant yield detractors as a consequence of occupying substantial die area, creating placement and routing blockages, and having stringent Vccmin and power integrity requirements. Achieving timing-correctness for embedded memories in advanced nodes is costly (e.g., closing the design at multiple (logic-memory) cross-corners). Further, multiphysics (e.g., crosstalk, IR, etc.) signoff analyses make early understanding and prediction of timing (-correctness) even more difficult. With long tool and design closure subflow runtimes, design teams need improved prediction of embedded memory timing failures, as early as possible in the implementation flow. In this work, we propose a learning-based methodology to perform early prediction of timing failure risk given only the netlist, timing constraints, and floorplan context (wherein the memories have been placed). Our contributions include (i) identification of relevant netlist and floorplan parameters, (ii) the avoidance of long P&R tool runtimes (up to a week or even more) with early prediction, and (iii) a new implementation of Boosting with Support Vector Machine regression with focus on negative-slack outcomes through weighting in the model construction. We validate accuracy of our prediction models across a range of “multiphysics” analysis regimes, and with multiple designs and floorplans in 28FDSOI foundry technology. Our work can be used to identify which memories are “at risk”, guide floorplan changes to reduce predicted “risk”, and help refine underlying SoC implementation methodologies. Experimental results in 28nm FDSOI technology show that we can predict P&R slack with multiphysics analysis to within 253ps (average error less than 10ps) using only post-synthesis netlist, constraints and floorplan information. Our predictions are 40% more accurate than - he predictions (worst-case error of 358ps and average error of 42ps) of a nonlinear Support Vector Machine model that uses only post-synthesis netlist information.
机译:嵌入式记忆对于复杂的片上系统(SOC)产品的成功或失败至关重要。由于占用大量模具区域,创建放置和路由堵塞,并且具有严格的VCCMIN和电力完整性要求,它们可以是显着的产量折断剂。在高级节点中实现对嵌入存储器的定时正确性(例如,在多个(逻辑存储器)交叉角上关闭设计)。此外,多发性(例如,串扰,IR等)签署分析提前了解和预测时序(-Corretcness)更加困难。通过长工具和设计闭合子流运行时,设计团队需要提高对嵌入式内存定时故障的预测,尽早在实现流程中尽早。在这项工作中,我们提出了一种基于学习的方法,以便仅给出仅包括网表,时序约束和地板上下文的时序失败风险的早期预测(其中已经放置了存储器)。我们的贡献包括(i)识别相关的网表和平面图参数,(ii)避免使用早期预测的Long P&R工具运行时间(最多一周或更多),并通过支持向量机提升的新实施回归通过在模型建设中通过加权来重点放在负面松弛结果上。我们验证了我们在一系列“多发性”分析制度中的预测模型的准确性,并在28FdSoI铸造技术中具有多种设计和平面平面图。我们的工作可用于确定哪些存储器是“危险”,导游平面图更改以减少预测的“风险”,并帮助改进潜在的SOC实施方法。 28nm FDSOI技术的实验结果表明,我们可以使用综合后的NetList,约束和平面图信息预测多态度分析的P&R松弛到253ps(平均误差小于10ps)。我们的预测比仅使用后综合后网列表信息的非线性支持向量机模型(358PS的358ps误差和42ps的平均误差)的预测更准确。

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