An optical area I/O enhanced FPGA with 256 optical channels per chip

摘要

It is our goal to demonstrate the viability of massively parallel optical interconects between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Fiekd-programmable gate arrays (FPGA) have been identified as a class of general-purose very large scale intergration components that could benefit from the massive introduction of state-of-the art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 x 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three-chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discussed the general architecture of our demonstrator system and the realization of th optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.