Algorithm and Architecture of a 1V Low Power Hearing Instrument DSP

摘要

This paper presents a 1 V digital signal processor used in the Danalogic hearing aid manufactured by GN Danavox. The processor is the first general purpose programmable used in behind-the-ear and in-the-ear hearing aid applications. It is integrated with memories, in a 0.5#mu# CMOS process with standard thresholds. At 2 MHz processing speed, the processor consumes 800#mu#A from a single cell battery. Using a dual multiply-accumulate architecture, the processor executes a 256 point block floating-point FFT in just 2900 instruction cycles.