Multiple and Parallel Execution Units in Digital Signal Processors

摘要

The paper introduces a new trend in fixed-point DSPs architecture. It focuses on adding execution units and parallel operations. The paper reveals the difficulties the architecture-designers encounter while dealing with this issue, such as the memory-computation unit connectivity and operating the different arithmetic units. Solutions and examples are presented, taking into consideration the performance, power consumption, area and complexity. Discussions on related issues, such as code compactness, are included, as well as architecture approaches with regard to the instruction word (VLIW, PIW). The paper includes examples of new DSPs including DSP Group's new generations, PalmDSPCore™ and TeakDSPCore™.