Physical design methodology for analog circuitsin a system-on-a-chip environment

摘要

This talk reviews some of the issues that are unique to analog Integrated Circuit (IC) design. These issues become more acute as the process geometries shrink and the complexity of the IC increases. In so-called "Systems on a Chip" (SOCs), the analog circuitry is combined with large amounts of logic on the same die. The switching noise complicates the design of high-accuracy circuits.In addition, analog circuits need a certain amount of silicon area to work well. This area does not necessarily scale much as the process geometries get smaller. In order for the analog circuitry to remain cost-competitive, very careful optimization of the layout is critical. For all these reasons, new specialized design methodologies are needed. New tools are emerging, which are specifically aimed at optimizing the layout of the analog circuitry at the same time as the schematic, taking in account the environment. An overview of these tools is given.