A VLSI ARCHITECTURE OF A DECODER FOR TRELLIS CODED MODULATION USING CONSTELLATIONS DESIGNED FOR THE RAYLEIGH CHANNEL

摘要

New N-dimensional constellations for the Rayleigh fading channel have been described in [4,5,6]. These constellations provide a diversity of order N and a gain of 10 dB to 14.5 dB at a BER of 10-3 when compared to 16-QAM modulations. The decoding of a 4-dimensional 4096 points constellation seems unrealistic, even with today's VLSI technology. This paper proposes algorithmic simplifications,which allow us to decrease the complexity of the implementation to a reasonable level. In addition, an architecture is also proposed for a VLSI decoder for a 34 Mb/s digital HDTV signal, and its complexity is evaluated.