Systolic Architecture for the VLSI Implementation of High-Speed Staged Decoders/Quantizers

摘要

This article deals the Systolic Array Implementation of a block-oriented algorithm known as Staged Decoding. The Staged Decoding Algorithm is a suboptimal general procedure for decoding a class of signal apaces codes and lattices obtained through Generalized Concatenation construction [1]. By exploiting the trellis representation of block codes and the algebraic formulation of the Viterbi Algorithm of [4]. we derive a very efficient Symbol-level ipelined architecture of the Staged Processor. In order to show the strength of our architecture,we have considered the implementation of a Staged Decoder for the 8-PSK BCM scheme with block-length 8 and rate 1 bit/dimension proposed in [5]. We have obtained a decoding rate of more than 700 Mbps with an associated hardware complexity of less than 30 Kgates (CMOS, 0.8μm).