DESIGN TEST OF MEMORY MANAGEMENT UNIT AND CACHE CONTROLLER CHIP

摘要

A design and test of memory management unit and cache controller (MMU/CC)chip for the Multiprocessor Architecture Reconciling Symbolic with numerical processing(MARS)are presented in this paper.MMU/CC can provide the memory access requirement of the MARS system for one load per cycle in the absence of cache miss,TLB miss,exception or interrupt.Not only the cache and memory operations are supported,but also an invalidation cache coherence protocolis embedded.The MMU/CC chip has 66290 transistors and 144 pins.The die size is 8653 μm * 7114 μm.We take a detailed look at critical issues of the design trade-offs,floor-planning,and testing.