A NEW REPRESENTATION FOR PROGRAMMABLE LOGIC ARRAYS TO FACILITATE TESTING AND LOGIC DESIGN

摘要

In this paper,we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs).Through this graph model, most realistic PLA faults, including crosspoint,stuck-at,break and bridging faults,can be modeled.The work of diagnosis and test generation is thus simplified. Also many logic design problems such as folding,minimization and decomposition can be done using this representation.