A MACHINE-DESCRIPTION TABLE BASED INSTRUCTION SCHEDULER FOR IMPROVING PIPELINE EXECUTION PARALLELISM ON QHRC RISC SYSTEM

摘要

This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system,having a (3-5)stages pipeline structure. It would provide considerable flexibility for instruction scheduling,improving execution efficiency for rapidly upgrading RISC machines. And, using this inetruction schedule as a tool,the effect of several methods for solying instruction interlock problem has been analyzed. Finally,a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is giyen.The algorithm complexity is O(n2).