Better than one operation per clock (panel)

摘要

In the 1980s, considerable advances were made in both software and hardware technology, and CPUs that can issue no more than one operation per clock cycle are rapidly approaching this barrier. Further improvements to uniprocessor performance can be obtained by enhancing the architecture of the CPU to allow multiple operations to be issued in a single clock cycle. The focus of this panel is to discuss three architectural approaches to issuing multiple operations per cycle: (i) vector instructions, (ii) very long instruction words (VLIW), and (iii) superscalar execution. We have asked the panelists to address several issues from the vantage point of their preferred architectural approach. These include:

What operation set parallelism are you trying to exploit (as distinct from instruction set parallelism)?

How does mapping from your operation set to your instruction set enhance or restrict the ability to support this parallelism?

What are the performance optimization responsibilities of the compiler?

How well does your architecture tolerate possible run time uncertainties (cache miss, resource conflicts, dependencies, …) in the context of uniprocessor or multiprocessor systems?

What are the inherent advantages/disadvantages of your architectural approach over the others?

What further enhancements do you envision in the future? How will these affect the choice of architectural approach?