Optimal Placement of Read Thresholds for Coded NAND Flash Memory

摘要

Recent advances in the flash memory technology call for more efficient error-correction codes (ECCs) than the conventional, yet very popular, ones such as BCH codes. The ability to make multiple voltage reads allows one to estimate soft values at the time of decoding, which in turn makes soft-decision ECCs such as LDPC codes a suitable candidate for implementation in flash memories. On the other hand, fully utilizing the potential of soft decision based codes demands higher precision memory sensing, which introduces a trade-off between the read latency and the error probability. In this paper, we explore and compares two approaches to optimize the positioning as well as the number of read (word-line) voltages for a specified program/erase (PE) cycle.In the first approach, we aim for selecting those read thresholds that maximize the mutual information (MMI) of the equivalent discrete memoryless channel. By utilizing conventional optimization methods such as the gradient descent (GD), we are able to find the optimal read locations for any number of read probes. Our simulation results show that ~20 reads are effective. Next, we redesign our optimization problem to take the LDPC code structure into account. To do so, we use discretized density evolution (DDE) as a proxy for bit error rate (BER), which serves as our cost function in the GD search. To overcome the problem of local minima, we propose a two-step optimization: MMI for coarse optimization, followed by DDE for fine optimization. Simulation results confirm the effectiveness of this method.¹