VLSI IMPLEMENTATIONS OF ATM BUFFER MANAGEMENT

摘要

An architecture is introduced for a semishared buffer containing multiple FIFO queues.The simple and fast FIFO stack approach is generalized to allow overlapping,leading to memory efficiencies similar to those of complex,fully-shared architectures.A comparison is made of performance and VLSI implementation costs across the range of separated,semi-shared,and fully-shared buffers.