Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications

摘要

A method is presented for estimating the maximum operating speed of NMOS self-testing circuits designed using the BILBO technique. The unique feature of this method is that the speed estimation is based only on parameters of the original design (without built-in test logic) and parameters describing the BILBO modules. Thus, a computer-aided optimization of a self-testing structure with respect to area/speed criteria can be performed without the necessity of laying out multiple self-testing versions of the original design and running timing simulation on each one.