A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning

摘要

This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 ¿m CMOS process. The design approach is based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range. PLL techniques, involving a 8.5 MHz controlled oscillator that matches a specific part of the filter, are used to realize on-chip automatic tuning. The complete circuit features 71 dB dynamic range and consumes only 16 mW from a single 5 V supply.