Implementation of On-Chip and On-Package Reactive Equalizer to Minimize Inter-symbol Interference (ISI) and Jitter from Frequency Dependent Attenuation

摘要

In this paper, on-chip and on-package reactive equalizer schemes that minimize inter-symbol interference (ISI) and jitter are proposed. The proposed reactive equalizers are designed and optimized in a frequency domain for 3 Gbps signaling on a transmission line with frequency dependent loss and parasitic capacitance. The proposed reactive equalizer was implemented using a 0.18um CMOS process, and verification of improvements in the signal quality was performed via simulation and measurement of the time domain reflection and an eye diagram.