Minimum test patterns for residue networks

摘要

Residue networks are logic trees consisting of residue gates which calculate the modulo-m sum of two or more inputs. The principal result of this paper is that for a single output residue network consisting of modulo-m gates having n or less inputs each, the required number of test patterns is mn, provided the gates are of a particular logical construction. This represents a minimum number of test patterns since that is exactly the number of test patterns required for a complete functional test of a single modulo-m gate with n inputs.

In the next section, an application of the method described in this paper is briefly illustrated. The properties of residue gates which are necessary and sufficient for the use of this method and various means for generating the test patterns are described in the remaining sections.