Design of a Third Order Self Biased Adaptive Bandwidth Phase Lock Loop

摘要

The present work shows a feasible circuit realization of the third-order self-biased adaptive bandwidth PLL. It is shown that the system is stable for a wide capture range. It was also demonstrated that the third-order PLL performs improvement in (a) jitter, (b) settling time, and (c) undershoot/overshoot transients. Even though the circuit was not designed optimally for power, the third-order system exhibits these performance improvements over the second-order system only on a marginal increase of 10% in its power consumption.