A Design of 14-bits 驴驴 ADC and DAC for CODEC Applications in 0.18 驴 m CMOS process

摘要

This paper presents a sigma-delta modulation ADC (analog-to-digital converter) and DAC (digital-to-analog converter) for CODEC applications using 0.18 mum CMOS process. In the ADC parts, two sigma-delta modulators with 84 dB SNR are designed for the stereo applications, and their outputs are merged at the digital domain before decimation filter. Digital decimation filter is integrated with the analog sigma-delta modulators for the full ADC operation. In the DAC parts, the digital data is first processed at the interpolator filters, and modulated by the following sigma-delta modulators. To reduce the mismatch effect of the following DAC, the dynamic element matching method is proposed in this paper. It is designed with 0.18 mum CMOS process. The simulated SNR is about 100 dB. and the power consumption is 40 mA.