A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process

摘要

This paper presents a 14-bit 250 MS/s ADC fabricatedudin a 180 nm CMOS process, which aims at optimizing itsudlinearity, operating speed, and power efficiency. The implementedudADC employs an improved SHA with parasitic optimized bootstrappedudswitches to achieve high sampling linearity over a wideudinput frequency range. It also explores a dedicated foregroundudcalibration to correct the capacitor mismatches and the gainuderror of residue amplifier, where a novel configuration schemeudwith little cost for analog front-end is developed. Moreover, audpartial non-overlapping clock scheme associated with a highspeedudreference buffer and fast comparators is proposed toudmaximize the residue settling time. The implemented ADC isudmeasured under different input frequencies with a sampling rateudof 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30udMHz input, the measured SFDR and SNDR of the ADC is 94.7uddB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB forudup to 400 MHz. The measured DNL and INL after calibrationudare optimized to 0.15 LSB and 1.00 LSB, respectively, while theudWalden FOM at Nyquist frequency is 0.57 pJ/step.