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Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class Semi-Super Junction MOSFET

机译:600V级半超结MOSFET的n缓冲层(n-底部辅助层)的设计概念

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We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (VB), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750V, the RonA= 24.6m驴cm2, the maximum avalanche current density JAP=292A/cm2 (IAP=7.6A, EAS=1.25J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0脳l015cm-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high TBAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.
机译:我们报告了有关600V级Semi-SJ MOSFET的n缓冲层(n-BAL:n-底部辅助层)的详细实验结果,并通过比较特定导通与导通之间的权衡特性,讨论了设计优化。电阻(RonA)和击穿电压(VB),雪崩能力和体二极管特性首次出现。作为设计参数,在这项工作中改变了厚度比TBAL-比率和掺杂浓度NBAL。结果,获得了VB = 750V,RonA = 24.6m驴cm2,最大雪崩电流密度JAP = 292A / cm2(IAP = 7.6A,EAS = 1.25J / cm2)和柔软度= 0.277的结果。 TBAL比率的结构= 27%,而NBAL = 1.0×1015cm-3。演示结果表明,与PT(Punch Through)设计相比,NPT(非Punthrough)设计(具有较高的TBAL比率和较高的NBAL)实现了更大的雪崩能力和更柔和的反向恢复特性。

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